![modelsim pe student edition waveform of v file modelsim pe student edition waveform of v file](https://images.slideplayer.com/35/10333860/slides/slide_8.jpg)
axi_tb.files - testbench file sources for AXI cluster (for simulation only).ahb_tb.files - testbench file sources for AHB cluster (for simulation only).axi_top.files - synthesized file sources of AXI cluster.ahb_top.files - synthesized file sources of AHB cluster.core.files - all synthesized file sources of the SCR1 core.SCR1 source file lists of SCR1 can be found in. Sample program "Interrupt Service Routine" RISC-V Compliance platform specific source filesĮEMBC's CoreMark® benchmark platform specific source files RISC-V ISA tests platform specific source files
![modelsim pe student edition waveform of v file modelsim pe student edition waveform of v file](https://i.ytimg.com/vi/cu4G8RjEMf4/maxresdefault.jpg)
![modelsim pe student edition waveform of v file modelsim pe student edition waveform of v file](https://i.ytimg.com/vi/jmH7ZJO90mg/maxresdefault.jpg)
Repository contents FolderĬommon source files for RISC-V Compliance testsĬommon source files for EEMBC's CoreMark® benchmark
MODELSIM PE STUDENT EDITION WAVEFORM OF V FILE LICENSE
Open sourced under SHL-license (see LICENSE file) - unrestricted commercial use allowed.It is industry-grade and silicon-proven (including full-wafer production), works out of the box in all major EDA flows and Verilator, and comes with extensive collateral and documentation. SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore.